The present invention relates to a pattern generator which is employed in testing of logic circuit devices and which generates test data for input into the logic circuit device under test (hereinafter referred to as DUT) and correct data corresponding to the output of the logic circuit device based on the input of the test data, that is, expected value data.
With an increase in the integration density and in the logic depth of the logic circuit device, which usually comprises a plurality of relatively simplestructured internal logic circuits or combinational logic circuits, it will become more and more difficult to locate failures by the common traditional method of only applying test data to input terminals of the DUT and then checking data obtained from its output terminals because many steps are involved in processing of the input data, and it will also be difficult to generate the test pattern that insures a 100% failure detection. As a solution to this problem a logic design through the LSSD techniques has been proposed, for example, in U.S. Pat. No. 3,783,254. According to the LSSD techniques, flip-flops provided for latching the outputs of respective internal logic circuits in the DUT are arranged to be directly connectable to one another all in series, in response to a control signal, and individual test patterns are serially input into the series-connected flip-flops. Then the series connection is resolved into individuals and the test data thus input are applied to the subsequent internal or combinatorial logic circuits respectively connected to the flip-flops and the operation of the internal logic circuits is advanced by one clock. The results of their operations are input again into the flip-flops and they are connected again in series, after which their states are serially read out and, at the same time, new test data are serially input into the flip-flops and the read-out data is checked to see whether the corresponding internal logic circuit operated correctly. In this manner, the entire logic circuit device is tested.
Each of the successive test patterns to be used for the logic circuit device designed by such LSSD techniques is composed of N bits of the same number as the sum of the numbers of input and output terminals of the logic circuit device. In the test pattern for advancing the operation of the internal logic circuits in parallel (i.e. simultaneously) by one step, the N bit pattern consists of input data and expected value data, but during the periods in which test data is applied to the series-connected flip-flops and operation results are read out from the series connected flip-flops, only three bits in each N-bit test pattern, that is, one-bit test data for input to one end of the series connection of the flip-flops, expected value data for comparison with one-bit data that is read out from the other end of the series connection and one-bit control data for connecting the flip-flops in series, are effectively used, while the other remaining (N-3) bits are not used for test and are usually held unchanged. Conventionally, such N-bit test patterns are prestored at successive addresses of an N-bit-word pattern memory and read out in a sequential order.
It is, however, frequent during a test that only three bits in an N-bit word are actually used, as mentioned above, so that memory cells corresponding to (N-3) bits are not utilized efficiently. Since the number of such words in the pattern memory is very large, the efficiency of its utilization is very low. Further, since logic operation is advanced by one step after each serial application of data to all of the series-connected flip-flops, the length of the entire sequence of the test patterns becomes considerably long and it becomes necessary for subsequent test patterns to be transferred from a large-capacity pattern file to the pattern memory after each completion of reading out of all the patterns from the pattern memory. With this method, however, the number of transfers is large and much time is needed for testing the whole logic circuit device.
Moreover, even apart from the LSSD techniques, it may frequently happen, in testing of logic circuit devices, that the same procedure is repeated but some parts of the data used therefor differ for each step. In such a case, it has been conventional to store all the necessary test patterns in the pattern memory. Consequently, large quantities of data of the same contents are stored in the pattern memory, resulting in an uneconomic use of memory.